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1 ? acpi regulator/controller for dual channel ddr memory systems the isl6532a provides a complete acpi compliant power solution for up to 4 dimm dual channel ddr/ddr2 memory systems. included are both a synchronous buck controller and integrated ldo to supply v ddq with high current during s0/s1 states and standby current during s3 state. during s0/s1 state, a fully integr ated sink-source regulator generates an accurate (v ddq /2) high current v tt voltage without the need for a negative supply. a buffered version of the v ddq /2 reference is provided as v ref . an ldo controller is also integrated for agp core voltage regulation. the switching pwm controller drives two n-channel mosfets in a synchronous -rectified buck converter topology. the synchronous buck converter uses voltage- mode control with fast transient response. both the switching regulator and standby ldo provide a maximum static regulation tolerance of 2% over line, load, and temperature ranges. the output is user-adjus table by means of external resistors down to 0.8v. switching memory core output between the pwm regulator and the standby ldo during state transitions is accomplished smoothly via the internal acpi control circuitry. the nch signal provides synchronized switching of a backfeed blocking switch dur ing the transitions eliminating the need to route 5v dual to the memory supply. an integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to s0/s1 state from any sleep state. during s0 the pgood signal indicates v tt is within spec and operational. each output is monitored for under and overvoltage events. the switching regulator has overcurrent protection. thermal shutdown is integrated. features ? generates 3 regulated voltages - synchronous buck pwm controller with standby ldo - 3a integrated sink/source linear regulator with accurate vddq/2 divider reference. - glitch-free transitions during state changes - ldo regulator for 1.5v video and core voltage ? acpi compliant sleep state control ? integrated v ref buffer ? pwm controller drives low cost n-channel mosfets ? 250khz constant frequency operation ? tight output voltage regulation - all outputs: 2% over-temperature ? 5v or 3.3v down conversion ? fully-adjustable outputs with wide voltage range: down to 0.8v supports ddr and ddr2 specifications ? simple single-loop voltage-mode pwm control design ? fast pwm converter transient response ? under and overvoltage monitoring on all outputs ? ocp on the switching regulator ? integrated thermal shutdown protection ? qfn package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, thinner in profile ? pb-free available (rohs compliant) applications ? single and dual channel ddr memory power systems in acpi compliant pcs ? graphics cards - gpu and memory supplies ? asic power supplies ? embedded processor and i/o supplies ? dsp supplies ordering information part number part marking temp. range (c) package pkg. dwg. # isl6532acr* , ** isl 6532acr 0 to +70 28 ld 6x6 qfn l28.6x6 isl6532acrz* , ** (note) isl6532 acrz 0 to +70 28 ld 6x6 qfn (pb-free) l28.6x6 ISL6532AIRZ* (note) isl6532 airz -40 to +85 28 ld 6x6 qfn (pb-free) l28.6x6 *add ?-t? suffix for tape and reel. **add ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications note: these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 te rmination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products ar e msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2004, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6532a data sheet may 5, 2008 fn9099.5
2 fn9099.5 may 5, 2008 pinout isl6532a (28 ld qfn) top view gndp 5vsby gndq gndq vtt vtt vddq pgood phase drive2 fb2 gnda comp fb gndp lgate ugate p12v s5# s3# nch vddq vddq vttsns p5vsby ocset vref_out vref_in 1 2 3 4 5 6 7 21 28 27 26 25 24 23 22 8 9 10 11 12 13 14 gnd 29 20 19 18 17 16 15 isl6532a
3 fn9099.5 may 5, 2008 block diagram soft-start, pgood, comp ea1 pwm gnda ugate vtt(2) vttsns oscillator and fault logic fb comp vtt voltage reference uv/ov1 soft-start 0.800v 0.680v (-15%) lgate p12v pwm logic 0.920v (+15%) vref_in vddq(3) pgood reg s5# s3# s0/s3 5v por 5vsby pwm enable p5vsby nch gndq sleep, vddq s3 regulator ea2 12vcc fb2 drive2 vref_out 12v por s3 uv/ov3 phase 20 a ocset oc comp 250khz gndp uv/ov s0 { { r u r l disable 650 output impedance uv/ov2 + - + - + - + - + - + - + - +- + - + - isl6532a
4 fn9099.5 may 5, 2008 simplified power system diagram typical application - 5v or 3.3v input pwm 5vsby vtt isl6532a controller regulator 12v standby ldo v ref v tt + sleep state logic 5vsby/3v3sby slp_s3 slp_s5 linear controller q3 + v ddq v ddq q1 5v q2 + nch v agp 5vsby ugate fb comp isl6532a c bp lgate +12v vtt vtt + v tt + vref_in vref_out slp_s3 slp_s5 vttsns pgood +3.3v q3 + v ddq drive2 fb2 c out2 v ddq q1 2.5v c in l out + + q2 +5v or +3.3v nch ocset r ocset vddq gndq gndp gnda phase v agp 1.5v v ref c vddq_out c vtt_out v ddq q4 r nch s3# s5# 5vsby p5vsby p12v vddq vddq gndq isl6532a
5 fn9099.5 may 5, 2008 typical application - input from 5v dual gndp fb comp isl6532a +12v gnda vddq vtt vtt + v tt v ref vref_in vref_out slp_s3 slp_s5 vttsns pgood q3 + v ddq drive2 fb2 c out2 v ddq q1 2.5v c in l out + + q2 5v dual ugate lgate nch gndq phase ocset r ocset v agp 1.5v c vddq_out c vtt_out v ddq 5vsby c bp +3.3v 5vsby p5vsby p12v s3# s5# vddq vddq gndq isl6532a
6 fn9099.5 may 5, 2008 absolute maximum rati ngs thermal information 5vsby, p5vsby . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +7v p12v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +14v ugate, lgate, nch . . . . . . . . . . . . . . gnd - 0.3v to p12v + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 5vcc + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 recommended operating conditions supply voltage on 5vsby . . . . . . . . . . . . . . . . . . . . . . . . +5v 10% supply voltage on p12v . . . . . . . . . . . . . . . . . . . . . . . . +12v 10% supply voltage onp5vsby . . . . . . . . . . . . . . . . . . . . . . . +5v 10% commercial ambient temperature range. . . . . . . . . . 0c to +70c industrial ambient temperature range . . . . . . . . . . -40c to +85c junction temperature range. . . . . . . . . . . . . . . . . -40c to +125c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) qfn package . . . . . . . . . . . . . . . . . . . 32 5 maximum junction temperature (plastic package) . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. limits established by characteri zation and are not production tested. electrical specifications recommended operating conditions, industrial temperatur e range, unless otherwise noted. refer to block and simplified power system diagram s and typical application schematics parameter symbol test conditions min typ max units 5vsby supply current nominal supply current i cc_s0 s3# and s5# high, ugate/lgate open 3.00 5.25 7.25 ma i cc_s3 s3# low, s5# high, ugate/lgate open 3.50 - 5 ma i cc_s5 s5# low, s3# don?t care, ugate/lgate open 0.3 - 0.925 ma power-on reset rising 5vsby por threshold 4.00 - 4.35 v falling 5vsby por threshold 3.55 - 3.95 v rising p12v por threshold 10.0 - 10.6 v falling p12v por threshold 8.80 - 9.75 v oscillator and soft-start pwm frequency f osc commercial temperature range 220 250 280 khz pwm frequency f osc 200 240 280 khz ramp amplitude v osc -1.5- v error amp reset time t reset mechanical off/s5 to s0 6.5 - 10 ms vddq soft-start interval t ss mechanical off/s5 to s0 6.5 - 10 ms reference voltage reference voltage v ref commercial temperature range 0.784 0.800 0.816 v reference voltage v ref 0.780 0.800 0.820 v pwm controller error amplifier dc gain note 3 - 80 - db gain-bandwidth product gbwp note 3 15 - - mhz slew rate sr note 3 - 6 - v/ s isl6532a
7 fn9099.5 may 5, 2008 state logic s3# transition level v s3 -1.5- v s5# transition level v s5 -1.5- v pwm controller gate drivers ugate and lgate source i gate --0.8- a ugate and lgate sink i gate -0.8- a nch backfeed control nch current sink i nch nch = 0.8v - - 6 ma nch trip level v nch 9.0 9.5 10.0 v vddq standby ldo output drive current p5vsby = 5.0v - - 650 ma p5vsby = 3.3v - - 550 ma vtt regulator upper divider impedance r u -2.5- k lower divider impedance r l -2.5- k vref_out buffer source current i vref_out --2ma maximum v tt load current i vtt_max periodic load applied with 30% duty cycle and 10ms period using isl6532aeval1 evaluation board (see application note an1056) -3 - 3 a linear regulator dc gain note 3 - 80 - db gain bandwidth product gbwp note 3 9 - - mhz slew rate sr note 3 - 6 - v/ s drive2 high output voltage 10.0 10.2 - v drive2 low output voltage - 0.16 0.40 v drive2 high output source current -.5 -1.4 - ma drive2 low output sink current .85 1.3 - ma pgood pgood rising threshold v vttsns/ v vddq s0 - 57.5 - % pgood falling threshold v vttsns/ v vddq s0 - 45.0 - % protection ocset current source i ocset 15 20 22.5 a vddq ov level v fb /v ref s0 - 115 - % vddq uv level v fb /v ref s0 - 85 - % linear regulator ov level v fb2 /v ref s0 - 115 - % linear regulator uv level v fb2 /v ref s0 - 85 - % thermal shutdown limit t sd note 3 - 140 - c electrical specifications recommended operating conditions, industrial temperatur e range, unless otherwise noted. refer to block and simplified power system diagram s and typical application schematics (continued) parameter symbol test conditions min typ max units isl6532a
8 fn9099.5 may 5, 2008 functional pin description 5vsby (pin 2) 5vsby is the bias supply of the isl6532a. it is typically connected to the 5v standby rail of an atx power supply. during s4/s5 sleep states the isl6532a enters a reduced power mode and draws less than 1ma (i cc_s5 ) from the 5vsby supply. the supply to 5vsby should be locally bypassed using a 0.1 f capacitor. p12v (pin 25) p12v provides the gate drive to the switching mosfets of the pwm power stage. the v tt regulation circuit and the linear driver are also powered by p12v. p12v is not required except during s0/s1/s2 operation. p12v is typically connected to the +12v rail of an atx power supply. 5vsby (pin 11) this pin provides the v ddq output power during s3 sleep state. the regulator is capable of providing standby v ddq power from either the 5 vsby or 3.3vsby rail. it is recommended that the 5vsby rail be used as the output current handling capability of the standby ldo is higher than with the 3.3vsby rail. gnd, gnda, gndp, gndq (pins 1, 3, 4, 17, 29) the gnd terminals of the isl6532a provide the return path for the v tt ldo, standby ldo and switching mosfet gate drivers. high ground currents are conducted directly through the exposed paddle of the qfn package which must be electrically connected to the ground plane through a path as low in inductance as possible. gnda is the analog ground pin, gndq is the return for the vtt regulator and gndp is the return for the upper and lower gate drives. ugate (pin 26) ugate drives the upper (control) fet of the v ddq synchronous buck switching regulator. ugate is driven between gnd and p12v. lgate (pin 27) lgate drives the lower (synchronous) fet of the v ddq synchronous buck switching regulator. lgate is driven between gnd and p12v. fb (pin 15) and comp (pin 16) the v ddq switching regulator employs a single voltage control loop. fb is the negative input to the voltage loop error amplifier. the positive input of the error amplifier is connected to a precision 0.8v reference and the output of the error amplifier is connected to the comp pin. the v ddq output voltage is set by an external resistor divider connected to fb. with a properly selected divider, v ddq can be set to any voltage between the power rail (reduced by converter losses) and the 0.8v reference. loop compensation is achieved by connecting an ac network across comp and fb. the fb pin is also monitored for under and overvoltage events. phase (pin 20) connect this pin to the upper mosfet?s source. this pin is used to monitor the voltage drop across the upper mosfet for overcurrent protection. ocset (pin 12) connect a resistor (r ocset ) from this pin to the drain of the upper mosfet, r ocset , an internal 20 a current source (i ocset ), and the upper mosfet on-resistance (r ds(on) ). set the converter overcurrent (oc) trip point according to equation 1: an overcurrent trip cycles the soft-start function. vddq (pins 7, 8, 9) the vddq pins should be connected externally together to the regulated v ddq output. during s0/s1 states, the vddq pins serve as inputs to the v tt regulator and to the v tt reference precision divider. during s3 state, the vddq pins serve as an output from t he integrated standby ldo. vtt (pins 5, 6) the vtt pins should be connec ted externally together. during s0/s1 states, the vtt pins serve as the outputs of the v tt linear regulator. during s3 state, the v tt regulator is disabled. vttsns (pin 10) vttsns is used as the feedback for control of the v tt linear regulator. connect this pin to the v tt output at the physical point of desired regulation. vref_out (pin 13) vref_out is a buffered version of v tt and also acts as the reference voltage for the v tt linear regulator. it is recommended that a minimum capacitance of 0.1 f is connected between v ddq and vref_out and also between vref_out and ground for proper operation. vref_in (pin 14) a capacitor, c ss , connected between vref_in and ground is required. this capacitor and the parallel combination of the upper and lower divider impedance (r u ||r l ), sets the time constant for the start up ramp when transitioning from s3 to s0/s1/s2. the minimum value for c ss can be found using equation 2: i peak i ocset xr ocset r ds on () ------------------------------------------------- = (eq. 1) c ss c vttout v ddq ? 10 2a r u r l || ?? ------------------------------------------------ > (eq. 2) isl6532a
9 fn9099.5 may 5, 2008 the calculated capacitance, c ss , will charge the output capacitor bank on the v tt rail in a controlled manner without reaching the current limit of the v tt ldo. nch (pin 22) nch is an open-drain output th at controls the mosfet blocking backfeed from v ddq to the input rail during sleep states. a 2k or larger resistor is to be tied between the 12v rail and the nch pin. until the voltage on the nch pin reaches the nch trip level, the pwm is disabled. if nch is not actively utilized, it still must be tied to the 12v rail through a resistor. for systems using 5v dual as the input to the switching regulator, a time constant, in the form of a capacitor, can be added to the nch pad to delay start of the pwm switcher until the 5v dual has switched from 5vsby to 5vatx. pgood (pin 21) power good is an open-drain logic output that changes to a logic low if any of the three regul ators are out of regulation in s0/s1/s2 state. pgood will always be low in any state other than s0/s1/s2. slp_s5# (pin 24) this pin accepts the slp_s5# sleep state signal. slp_s3# (pin 23) this pin accepts the slp_s3# sleep state signal. fb2 (pin 18) connect the output of the external linear regulator to this pin through a properly sized resistor divider. the voltage at this pin is regulated to 0.8v. this pin is monitored for under and overvoltage events. drive2 (pin 19) connect this pin to the gate terminal of an external n-channel mosfet transistor. this pin provides the gate voltage for the linear regulator pass transistor. it also provides a means of compensating the error amplifier for applications requiring the tran sient response of the linear regulator to be optimized. functional description overview the isl6532a provides complete control, drive, protection and acpi compliance for a regulator powering ddr memory systems. it is primarily designed for computer applications powered from an atx power supply. a 250khz synchronous buck regulator with a precision 0.8v reference provides the proper core voltage to the syst em memory of the computer. an internal ldo regulator with the ability to both sink and source current and an externally available buffered reference that tracks the v ddq output by 50% provides the v tt termination voltage. the isl6532a also features an ldo regulator for 1.5v agp video and core voltage. acpi compliance is realized through the slp_s3 and slp_s5 sleep signals and through monitoring of the 12v atx bus. initialization the isl6532a automatically initializes upon receipt of input power. special sequencing of the input supplies is not necessary. the power-on reset (por) function continually monitors the input bias supply voltages. the por monitors the bias voltage at the 5 vsby and p12v pins. the por function initiates soft-start operation after the bias supply voltages exceed their por thresholds. acpi state transitions cold start (s4/s5 to s0 transition) at the onset of a mechanical start, the isl6532a receives it?s bias voltage from the 5v st andby bus (5vsby). as soon as the slp_s3 and slp_s5 have transitioned high, the isl6532a starts an internal counter. following a cold start or any subsequent s4/s5 state, state transitions are ignored until the system enters s0/s1. none of the regulators will begin the soft-start procedure until the 5v standby bus has exceeded por, the 12v bus has exceeded por and v nch has exceeded the trip level. once all of these conditions are met, the pwm error amplifier will first be reset by internally shorting the comp pin to the fb pin. this reset lasts for 2048 clock cycles, which is typically 8.2ms (one clock cycle = 1/f osc ). the digital soft-start sequence will then begin. the pwm error amplifier reference input is clamped to a level proportional to the soft-start voltage. as the soft-start voltage slews up, the pwm comparator generates phase pulses of increasing width that charge the output capacitor(s). the internal vtt ldo will also soft-start through the referenc e that tracks the output of the pwm regulator. the reference for the agp ldo controller will rise relative to the soft-start refe rence. the soft-start lasts for 2048 clock cycles, which is typically 8.2ms. this method provides a rapid and controlled output voltage rise. figure 1 shows the soft-start sequence for a typical cold start. due to the soft-start capacitance, c ss , on the vref_in pin, the s5 to s0 transition profile of the v tt rail will have a more rounded features at the start and end of the soft-start whereas the v ddq profile has distinct starting and ending points to the ramp up. by directly monitoring 12vatx and the slp_s3 and slp_s5 signals the isl6532a can achieve pgood status significantly faster than other devices that depend on latched_backfeed_cut for timing. active to sleep (s0 to s3 transition) when slp_s3 goes low with slp_s5 still high, the isl6532a will disable the v tt linear regulator and the agp ldo controller. the v ddq standby regulator will be enabled isl6532a
10 fn9099.5 may 5, 2008 and the v ddq switching regulator will be disabled. nch is pulled low to disable the backfeed blocking mosfet. pgood will also transition low. when v tt is disabled, the internal reference for the v tt regulator is internally shorted to the v tt rail. this allows the v tt rail to float. when floating, the voltage on the v tt rail will depend on the leakage characteristics of the memory and mch i/o pins. it is important to note that the v tt rail may not bleed down to 0v. the v ddq rail will be supported in the s3 state through the standby v ddq ldo. when s3 transitions low, the standby regulator is immediately enabled. the switching regulator is disabled synchronous to the switching waveform. the shut off time will range between 4s and 8s. the standby ldo is capable of supporting up to 650 ma of load with p5vsby tied to the 5v standby rail. the standby ldo may receive input from either the 3.3v standby rail or the 5v standby rail through the p5vsby pin. it is recommended that the 5v standby rail be used as the current delivery capability of the ldo is greater. sleep to active (s3 to s0 transition) when slp_s3 transitions from low to high with slp_s5 held high and after the 12v rail exceeds por, the isl6532a will enable the v ddq switching regulator, disable the v ddq standby regulator, enable the v tt ldo and force the nch pin to a high impedance state turning on the blocking mosfet. the agp ldo goes through a 2048 clock cycle soft-start. the internal short between the v tt reference and the v tt rail is released. upon release of the short, the capacitor on vref_in is then charged up through the internal resistor divider network. the v tt output will follow this capacitor charge up, and acting as the s3 to s0 transition soft-start for the v tt rail. the pgood comparator is enabled only after 2048 clock cycles, or typically 8.2ms, have passed following the s3 transition to a high state. figure 2 illustrates a typical state transition from s3 to s0. it should be noted that the soft-start profile of the v tt ldo output will vary according to the value of the capacitor on the vref_in pin. active to shutdown (s0 to s5 transition) when the system transitions from active (s0) state to shutdown (s4/s5) state, the isl6532a ic disables all regulators and forces the pgood pin and the nch pin low. v ddq overcurrent protection (s0 state) the overcurrent function protects the switching converter from a shorted output by using the upper mosfet on- resistance, r ds(on) , to monitor the current. this method enhances the converter?s efficiency and reduces cost by eliminating a current sensing resistor. the overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. a resistor (r ocset ) programs the overcurrent trip level (see typical application diagrams on page 4 and page 5). an internal 20 a (typical) current sink develops a voltage across r ocset that is referenced to the converter input voltage. when the voltage across the upper mosfet (also referenced to the converter input voltage) exceed s the voltage across r ocset , the over- current function initiates a soft-s tart sequence. the initiation of soft-start will affect all regulators. the v tt regulator is directly affected as it receives it?s reference from v ddq . the agp ldo will also be soft-started, and as such, the agp ldo voltage will be disabled while the v ddq regulator is disabled. figure 3 illustrates the protection feature responding to an overcurrent event. at time t0, an overcurrent condition is sensed across the upper mosfet. as a result, the regulator is quickly shutdown and the internal soft-start function begins producing soft-start ramps. the delay interval seen by the output is equivalent to three soft-start cycles. the fourth figure 1. typical cold start v tt v ddq 12vatx 2v/div 5vsby s3 s5 1v/div 500mv/div 500mv/div v agp 500mv/div 12v por soft-start initiates soft-start ends pgood comparator enabled 2048 clock cycles 2048 clock cycles pgood 5v/div figure 2. typical s3 to s0 state transition v tt v ddq 12vatx 2v/div s3 s5 500mv/div 500mv/div pgood 5v/div v agp 500mv/div v tt_float 12v por pgood comparator enabled 2048 clock cycles isl6532a
11 fn9099.5 may 5, 2008 internal soft-start cycle initiate s a normal soft-start ramp of the output, at time t1. the output is brought back into regulation by time t2 as long as the overcurrent event has cleared. had the cause of the overcurrent still been present after the delay interval, the overcurrent condition would be sensed and the regulator would be shut down again for another delay interval of three soft-start cycles. the resulting hiccup mode style of protection would co ntinue to repeat indefinitely. the overcurrent function will tr ip at a peak inductor current (i peak) determined by: where i ocset is the internal ocset current source (20 a typical). the oc trip point varies mainly due to the mosfet r ds(on) variations. to avoid overcurrent tripping in the normal operating load range, find the r ocset resistor from equation 3 with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for: ,where i is the output inductor ripple current. for an equation for the ripple current, see the section under component guidelines titled ?o utput inductor selection? on page 14. a small ceramic capacitor should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input voltage. overvoltage and undervoltage protection all three regulators are protected from faults through internal overvoltage and undervoltage detection circuitry. if the any rail falls below 85% of the targeted voltage, then an undervoltage event is tripped. an undervoltage will disable all three regulators for a period of 3 soft-start cycles, after which a normal soft-start is initiat ed. if the output is still under 85% of target, the regulators will continue to be disabled and soft-started in a hiccup mode until the fault is cleared. this protection feature works much the same as the vddq pwm overcurrent protection works. see figure 3. if the any rail exceeds 115% of the targeted voltage, then all three outputs are immediately disabled. the isl6532a will not re-enable the outputs until either the bias voltage is toggled in order to initiate a por or the s5 signal is forced low and then back to high. thermal protection (s0/s3 state) if the isl6532a ic junction temperature reaches a nominal temperature of +140c, all r egulators will be disabled. the isl6532a will not re-enable the outputs until the junction temperature drops below +110c and either the bias voltage is toggled in order to initiate a por or the slp_s5 signal is forced low and then back to high. shoot-through protection a shoot-through condition occurs when both the upper and lower mosfets are turned on simultaneously, effectively shorting the input voltage to ground. to protect from a shoot- through condition, the isl6532a incorporates specialized circuitry, which insures that complementary mosfets are not on simultaneously. the adaptive shoot-through pr otection utilized by the v ddq regulator looks at the lower gate drive pin, lgate, and the upper gate drive pin, ugate, to determine whether a mosfet is on or off. if the voltage from ugate or from lgate to gnd is less than 0.8v, then the respective mosfet is defined as being off and the other mosfet is allowed to turned on. this method allows the v ddq regulator to both source and sink current. since the voltage of the mosfet gates are being measured to determine the state of the mosfet, the designer is encouraged to consider the r epercussions of introducing external components between the gate drivers and their respective mosfet gates before actually implementing such measures. doing so may interfere with the shoot- through protection. time t1 t0 t2 500mv/div v ddq v agp v tt figure 3. v ddq overcurrent protection and v tt /v agp ldo under voltage protection responses internal soft-start function delay interval i peak i ocset x r ocset r ds on () ---------------------------------------------------- - = (eq. 3) i peak i out max () i () 2 ---------- + > isl6532a
12 fn9099.5 may 5, 2008 application guidelines layout considerations layout is very important in high frequency switching converter design. with power devices switching efficiently at 250khz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, ra diate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes these voltage spikes. as an example, consider the tu rn-off transition of the control mosfet. prior to turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is picked up by the lower mosfet. any parasitic inductance in the swit ched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide traces minimi zes the magnitude of voltage spikes. there are two sets of critical components in the isl6532a switching converter. the switch ing components are the most critical because they switch large amounts of energy, and therefore tend to generate larg e amounts of noise. next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. a multi-layer printed circuit board is recommended. figure 4 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the gate pins to the mosfet gates should be kept short and wide enough to easily handle the 1a of drive current. in order to dissipate heat generated by the internal v tt ldo, the ground pad, pin 29, should be connected to the internal ground plane through at least four vias. this allows the heat to move away from the ic and also ties the pad to the ground plane through a low impedance path. the switching components should be placed close to the isl6532a first. minimize the length of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper and lower mosfets and the load. the critical small signal components include any bypass capacitors, feedback components, and compensation components. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors should be located as close as possible to the fb pin with vias tied straight to the ground plane as required. feedback compensation - pwm buck converter figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck conv erter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). v ddq 5vsby island on power plane layer island on circuit plane layer l out c out1 c in v in_ddr key comp isl6532a ugate r 4 r 2 c bp fb drive2 gndp 5vsby figure 4. printed circuit board power planes and islands r 1 v agp fb2 c 2 via connection to ground plane c out3 load load q 1 v in_agp r 5 r 6 phase r 3 c 3 c 1 q 2 12v atx c bp gndp p12v q 3 lgate p5vsby vddq(3) vtt(2) c out2 load v ddq v tt nch gnd pad isl6532a
13 fn9099.5 may 5, 2008 the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the isl6532a) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. the following equations relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 5. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place 1 st zero below filter?s double pole (~75% f lc ). 3. place 2 nd zero at filter?s double pole. 4. place 1 st pole at the esr zero. 5. place 2 nd pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin - repeat if necessary. compensation break frequency equations figure 6 shows an asymptotic plot of the dc-dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 6. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the graph of figure 6 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45 . include worst case component variations when determining phase margin. feedback compensation - agp ldo controller figure 7 shows the agp ldo power and control stage. this ldo, which uses a mosfet as the linear pass element, requires feedback compensation to insure stability of the system. the ldo requires compensation because of the output impedance of the error amplifier. figure 5. voltage-mode buck converter compensation design and output voltage selection v ddq reference l o c o esr v in v osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 2 c 3 c 1 c 2 comp v ddq fb z fb isl6532a z in comparator driver detailed compensation components phase v e/a + - + - z in osc r 4 v ddq 0.8 1 r 1 r 4 ------ - + ?? ?? ?? = f lc 1 2 x l o x c o ------------------------------------------ - = f esr 1 2 x esr x c o ------------------------------------------- - = (eq. 4) f z1 1 2 x r 2 x c 2 ------------------------------------ = f z2 1 2 x r 1 r 3 + () x c 3 ------------------------------------------------------ - = f p1 1 2 x r 2 x c 1 x c 2 c 1 c 2 + --------------------- - ?? ?? ?? -------------------------------------------------------- - = f p2 1 2 x r 3 x c 3 ------------------------------------ = (eq. 5) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 20log f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / v osc ) modulator gain (r 2 /r 1 ) figure 6. asymptotic bode plot of converter gain closed loop gain isl6532a
14 fn9099.5 may 5, 2008 to properly compensate the ldo system, a 100k 1% resistor and a 680pf x5r ceramic capacitor, represented as r 10 and c 25 in figure 7, are used. this compensation will insure a stable system with an y mosfet giv en the following conditions: maximum bandwidth will be realized at full load while minimum bandwidth will be realized at no load. bandwidth at no load will be maximized as becomes closer to 10 s. output voltage selection the output voltage of the v ddq pwm converter can be programmed to any level between v in and the internal reference, 0.8v. an external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier, see figure 5. however, since the value of r 1 affects the values of the rest of the compensation components, it is advisable to keep its value less than 5k . depending on the value chosen for r 1 , r 4 can be calculated based on the equation 7: if the output voltage desired is 0.8v, simply route v ddq back to the fb pin through r 1 , but do not populate r 4 . the output voltage for the internal v tt linear regulator is set internal to the isl6532a to track the v ddq voltage by 50%. there is no need for external programming resistors. as with the v ddq pwm regulator, the agp linear regulator output voltage is set by means of an external resistor divider as shown in figure 7. for stability concerns described earlier, the recommended value of the feedback resistor, r 8 , is 249 . the voltage programming resistor, r 9 can be calculated based on the equation 8: component selection guidelines output capacitor selection - pwm buck converter an output capacitor is required to filter the inductor current and supply the load transient current. the filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (d i/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. ddr memory systems are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with ca se size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multip le electrolytic capacitors of small case size perform better than a single large case capacitor. output capacitor selection - ldo regulators the output capacitors used in ldo regulators are used to provide dynamic load current. the amount of capacitance and type of capacitor should be chosen with this criteria in mind. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. th e inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: drive2 fb2 isl6532a v agp v ddq figure 7. compensation and output voltage selection of the linear 650 r 9 r 10 c 25 + - 0.8v + output impedance r 8 reference esr c out r load v agp 0.8 1 r 8 r 9 ------ - + ?? ?? ?? = c out esr ? 10 s > = r fb r 8 249 == (eq. 6) r 4 r1 0.8v v ddq - 0.8v ----------------------------------- - = (eq. 7) r 9 r 8 0.8v v agp - 0.8v ---------------------------------- - = (eq. 8) i= v in - v out fs x l v out v in v out = i x esr x (eq. 9) isl6532a
15 fn9099.5 may 5, 2008 increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the isl6532a will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current le vel. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection - pwm buck converter use a mix of input bypass capaci tors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed ea ch time the upper mosfet turns on. place the small cerami c capacitors physically close to the mosfets and between the drain of upper mosfet and the source of lower mosfet. the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. for most cases, the rms current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. the maximum rms current required by the regulator may be closely approximated through equation 11: for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor su rge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. mosfet selection - pwm buck converter the isl6532a requires 2 n-channel power mosfets for switching power and a third mosfet to block backfeed from v ddq to the input in s3 mode . these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor. t he switching losses seen when sourcing current will be different from the switching losses seen when sinking current. when sourcing current, the upper mosfet realizes most of the switching losses. the lower switch realizes most of the switching losses when the converter is sinking current (see the following equations). these equations assume linear voltage-current transitions and do not adequately model power loss due the reverse- recovery of the upper and lower mosfet?s body diode. the gate-charge losses are dissipated in part by the isl6532a and do not significantly heat the mosfets. however, large gate-charge increases th e switching interval, t sw which increases the mosfet switchi ng losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package ther mal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. t rise = l x i tran v in - v out t fall = l x i tran v out (eq. 10) i rms max v out v in ------------- - i out max 2 1 12 ------ v in - v out lf s ----------------------------- v out v in ------------- - ?? ?? 2 + ?? ?? = (eq. 11) p lower = io 2 x r ds(on) x (1 - d) where: d is the duty cycle = v out / v in , t sw is the combined switch on and off time, and f s is the switching frequency. approximate losses while sourcing current approximate losses while sinking current p lower io 2 r ds on () 1 - d () 1 2 -- - io ? v in t sw f s + = p upper io 2 r ds on () d 1 2 -- - io ? v in t sw f s + = p upper = io 2 x r ds(on) x d (eq. 12) isl6532a
16 fn9099.5 may 5, 2008 mosfet selection - agp ldo the main criteria for selection of the linear regulator pass transistor is package selection for efficient removal of heat. select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. the power dissipated in the linear regulator is: where i o is the maximum output current and v out is the nominal output voltage of the linear regulator. isl6532a application circuit figure 8 shows an application circuit utilizing the isl6532a. detailed information on the circuit, including a complete bill- of-materials and circuit board description, can be found in application note an1056. p linear i o v in - v out () ? (eq. 13) figure 8. ddr sdram and agp volt age regulator using the isl6532a 10.0k 1 f 5vsby ugate fb comp isl6532a c 17,18 lgate vcc12 vtt vtt + v tt vref_in vref_out vttsns pgood +3.3v q 4 + v ddq drive2 fb2 v ddq q 1,3 2.5v 15a max + + q 2,4 vcc5 nch ocset vddq gndq gndp gnda phase v agp 1.5v v ref v ddq q 5 gndq vddq vddq gndp 5vsby p5vsby p12v slp_s5 slp_s3 s5# s3# pgood c 16 r 2 1 f l 1 2.1 h l 2 2.1 h 4.99k r 1 c 19 0.47 f c 22 1000pf 8.87k r 7 c 6-8 c 9-12 1800 f 22 f 6.8nf c 14 825 r 6 c 15 c 13 r 5 r 4 r 3 22.6 1.74k 19.1k 56nf 1000pf 680pf c 25 r 10 100k r 9 287 r 8 249 220 f c 23 1 f c 24 1.25v + v ddq c 20 220 f c 21 220 f c 26 0.1 f c 27 0.1 f c 1-3 2200 f c 4,5 1 f isl6532a
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9099.5 may 5, 2008 isl6532a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l28.6x6 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vjjc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 6.00 bsc - d1 5.75 bsc 9 d2 3.95 4.10 4.25 7, 8 e 6.00 bsc - e1 5.75 bsc 9 e2 3.95 4.10 4.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n282 nd 7 3 ne 7 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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